1. Field of the Invention
The present invention relates to a semiconductor memory device of a hierarchical bit line structure where main bit lines are formed above sub-bit lines. More particularly, the present invention relates to a semiconductor memory device capable of high-speed accessing while suppressing an increase in the chip area.
2. Description of the Related Art
Conventional semiconductor memory devices (hereinbelow, simply referred to as the "memories") employ a hierarchical bit line method to reduce the capacitance ratio of bit lines for achieving high-speed accessing.
A memory of the hierarchical bit line structure is disclosed in Japanese Laid-Open Publication No. 60-253096, where an independent data transfer line is separately provided along a bit line to which a plurality of memory cells are connected. The bit line is divided into a plurality of portions, which are connected to the data transfer line via respective transfer gates, so as to improve the capacitance ratio of the bit lines to a memory capacitance of a DRAM and thus shorten a read cycle.
Non-volatile memories include flash EEPROMs and mask ROMs. As a conventional example of such ROMs, a mask ROM of the hierarchical bit line structure is proposed in Japanese Laid-Open Publication No. 6-104406.
Referring to FIGS. 17 and 18, the conventional mask ROM will be described. FIG. 17 illustrates a portion of an equivalent circuit of the mask ROM, and FIG. 18 illustrates a portion of a layout pattern of the mask ROM. Sub-bit lines (e.g., SB11 to SB17; herein-below, collectively referred to as "sub-bit lines SB") are formed on a semiconductor substrate (not shown) in parallel with one another in a column direction. The sub-bit lines SB are made of a diffusion layer formed on the semiconductor substrate. The conductivity type of the diffusion layer is opposite that of the semiconductor substrate.
A plurality of word lines (e.g., WL101 to WL132; hereinbelow, collectively referred to as "word lines WL") are formed on the semiconductor substrate in a row direction crossing the sub-bit lines SB via an insulating film. The word lines WL are made of polysilicon, for example, as shown in FIG. 17.
Memory cell transistors (e.g., M1 to M7; herein-below, collectively referred to as "memory cells M") are formed between the adjacent sub-bit lines SB. Each of the memory cells M constitutes a transistor where the adjacent sub-bit lines are used as the source or the drain, the word line is used as the gate electrode, and the region between the source and the drain located under the gate electrode is used as the channel. Such memory cells M are arranged in a matrix over the entire semiconductor substrate.
Auxiliary conductive regions (e.g., BB11, BB12, BB21, BB22; hereinbelow, collectively referred to as "auxiliary conductive regions BB") are formed at ends of the sub-bit lines SB. The auxiliary conductive regions BB have the same conductivity type as the sub-bit lines SB.
Bank selection transistors (e.g., TB11 to TB18; hereinbelow, collectively referred to as "bank cells TB") are formed between the auxiliary conductive regions BB and the sub-bit lines SB. Each of the bank cells TB constitute a transistor where the combination of the auxiliary conductive region BB and the sub-bit line SB is used as the source/drain, and a bank selection line (e.g., BS11 to BS14; hereinbelow, collectively referred to as "bank selection lines BS") is used as the gate electrode. The bank selection lines BS are made of polysilicon, for example, and arranged in the row direction.
The auxiliary conductive regions BB are connected to main bit lines (e.g., MB1 to MB4; hereinbelow, collectively referred to as "main bit lines MB") via contacts (e.g., CT11, CT12, CT21, CT22; hereinbelow, referred to as "contacts CT").
Herein, groups of rows of the sub-bit lines SB arranged in parallel with one another and the corresponding auxiliary conductive regions BB connected to the sub-bit lines SB constitute banks (e.g., BNK0 to BNK2; hereinbelow, collectively referred to as "banks BNK").
In the mask ROM shown in FIG. 17, the sub-bit lines SB of each bank BNK are connected to the main bit lines MB via the bank cells TB, so that they are selectively activated with the main bit lines MB via the bank selection lines BS. The main bit lines MB are connected to a circuit outside the memory cell array, such as sense amplifiers, via a column selection circuit 1.
Hereinbelow, the operation of the above conventional mask ROM will be described, taking as an example the case where the semiconductor substrate has a p-type conductivity and the sub-bit lines SB and the auxiliary conductive regions BB have an n.sup.+ -type conductivity.
First, the potential of predetermined bank selection lines BS and a predetermined word line WL are set at a high level, to select the bank cells TB and the memory cell M which use the predetermined bank selection lines BS and the predetermined word line WL, respectively, as the gate electrodes thereof.
The threshold value of the memory cell M can be set by adjusting the amount of boron ions implanted in the channel region thereof located under the gate electrode, for example. Since an ion-implanted memory cell M has an increased threshold voltage, by implanting a predetermined amount of ions, the memory cell M can be kept in an OFF state even when the gate potential is turned to a high level (for example, an OFF cell as shown in FIG. 18 described hereinbelow). On the contrary, when no ions are implanted, the threshold voltage is set so that the memory cell M turns to an ON state when the gate potential is turned to a high level (an ON cell). The portions of the bank selection lines BS which are not used for the bank cells TB are ion-implanted to be set at the OFF state.
One memory cell M of one bank BNK is selected by a row selection circuit 2 in the following manner. The word line WL used as the gate electrode of the memory cell M and the bank selection lines BS used as the gate electrodes of the bank cells TB connected to the adjacent sub-bit lines BS used as the source/drain of the memory cell M are set at a high level.
For example, data stored in the memory cell M2 is read by setting the word line WL132 and the bank selection lines BS11 and BS14 at a high level, while setting the others at a low level, to select the bank cells TB11 and TB16. The sub-bit lines SB12 and SB13 are connected to the main bit lines MB2 and MB1 via the contacts CT11 and CT21, respectively. The main bit lines MB1 and MB2 are selectively connected to data lines (not shown) via the column selection circuit 1. In this way, data stored in the memory cell M2 selected through the above signal transmission route can be read.
In the above conventional mask ROM, one bank BNK is constituted of a plurality of columns of memory cells M formed between the adjacent sub-bit lines SB arranged in the row direction. A matrix-shaped memory cell array is constituted of a plurality of such banks BNK arranged in the column direction, where the auxiliary conductive regions BB are shared by the adjacent banks.
In each bank BNK, every two sub-bit lines SB are connected to one main bit line MB via the bank cells TB. Every adjacent sub-bit lines SB are connected to different main bit lines MB at opposite ends of the bank BNK via the bank cells TB. The two different main bit lines MB are connected to data lines via the column selection circuit 1. One of the data lines is connected to a low potential while the other is connected to a high potential. By detecting the difference in current between the two data lines, the state of the memory cell M can be read as binary information.
Hereinbelow, for easy understanding, one of the two main bit lines MB which is connected to a low potential is referred to as a "main ground line MB", and the sub-bit line SB connected to the main ground line MB is referred to as a "sub-ground line SB". The main bit lines are denoted by odd numbers (e.g., MB1, MB3) while the main ground lines are denoted by even numbers (e.g., MB2, MB4). The sub-bit lines are denoted by odd numbers (e.g., SB11, SB13) while the sub-ground lines are denoted by even numbers (e.g., SB12, SB14).
Since the above mask ROM has a hierarchical bit line structure, only one sub-bit line SB associated with the memory cell M to be accessed is activated with the main bit line MB via the bank cell TB. Other sub-bit lines SB are disconnected from the main bit line MB by the bank cells TB. This reduces the load of the main bit line MB, thereby allowing for high-speed accessing.
With the recent achievement of high-speed micro-processor units (MPUs), the request for high-speed semiconductor memories has been increasingly intensified and a variety of improvements have been made.
For example, a memory cell array is divided into a plurality of blocks in the column or row direction to reduce the length of bit lines or word lines, thereby reducing the loads of these lines to achieve high-speed accessing.
However, the above method has the following problem. When the memory cell array is divided in the direction of the word lines, row selection circuits are required for respective blocks for selecting the word lines. This markedly increases the chip area. Likewise, when the memory cell array is divided in the direction of the bit lines, column selection circuits and sense amplifiers are required for respective blocks for selecting the bit lines. This also markedly increases the chip area.
In the mask ROM of the conventional hierarchical bit line structure, the load of the main bit line mostly originates from junction capacitances at the source/drain diffusion regions of the bank cells and junction capacitances of the auxiliary conductive regions. An effective way to reduce the junction capacitances is by increasing the number of memory cells connected to each sub-bit line. However, as the sub-bit line is longer, the diffusion resistance increases, increasing the load of the main bit line and thus reducing the accessing speed.
More specifically, in the mask ROM of the conventional hierarchical bit line structure, one main bit line is provided for every two sub-bit lines. In general, interconnections are more difficult to be arranged on a semiconductor substrate with a higher density when they are formed from a higher-level layer due to steps generated in the fabrication process. For this reason, the design rule for the main bit lines which are higher-level metal interconnections is stricter than the design rule for the sub-bit lines which are formed as buried diffusion regions in the semiconductor substrate. It is therefore difficult to additionally form interconnections from the same layer of the main bit lines in parallel therewith in the above conventional structure. In the conventional structure, if the number of sub-bit lines connected to one main bit line is increased in one bank, the number of main bit lines with respect to the sub-bit lines can be reduced. In this case, however, as shown in FIG. 19, the number of bank selection lines in one bank increases as the number of sub-bit lines connected to the main bit line increases. This increases the chip area for the memory cell array.